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mpq2166 6v, dual 2a/2a or 3a/1a, low quiescent current, synchronous buck with pg and ss aec-q100 qualified mpq2166 rev. 1.11 www.monolithicpower.com 1 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the mpq2166 is an internally compensated, dual, pwm, synchronous, step-down regulator that operates from a 2.7v to 6v input and generates an output voltage as low as 0.6v. the mpq2166 can be configured as a 2a/2a or 3a/1a output current regulator and is ideal for powering portable equipment that runs on a single-cell lithium-ion (li+) battery due to a low 60a quiescent current. the mpq2166 integrates dual, 55m ? , high-side switches and 20m ? synchronous rectifiers for high efficiency without an external schottky diode. the mpq2166 has peak-current-mode control and internal compensation and is capable of low dropout configurations. both channels can operate at 100% duty cycle. full protection features include cycle-by-cycle current limit and thermal shutdown. the mpq2166 requires a minimum number of readily available, standard, external components and is available in qfn-18 (2mmx3mm) and qfn-18 (2.5mmx3.5mm) packages. features ? 2.7v to 6v operating input range ? 2a/2a or 3a/1a continuous current ? 55m ? /20m ? r ds(on) ? programmed frequency up to 3mhz ? external sync clock up to 3mhz ? 180 o phase shifted operation ? pg indicators ? external ss and track ? adjustable advanced asynchronous mode (aam) or forced continuous conduction mode (ccm) ? peak efficiency >90% ? output adjustable from 0.6v to vin ? 100% duty cycle operation ? 60a quiescent current ? cycle-by-cycle over-current protection (ocp) ? short-circuit protection (scp) with hiccup mode and valley current detection ? thermal shutdown ? available in qfn-18 (2mmx3mm) and qfn- 18 (2.5mmx3.5mm) packages ? available in aec-q100 grade-1 applications ? small/handheld devices ? dvd drivers ? smartphones and feature phones ? battery-powered devices ? portable instruments a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. fo r mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 2 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application i out (ma) efficiency vs. load current v out1 =1.8v, aam, one channel on 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 v in =2.7v v in =3.6v v in =5v l=1.5uh fsw=2.25m
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 3 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking mpq2166gd qfn-18 (2mmx3mm) see below mpq2166gd-aec1 ** qfn-18 (2mmx3mm) mpq2166gde-aec1 *** qfn-18 (2mmx3mm) mpq2166grh qfn-18 (2.5mmx3.5mm) MPQ2166GRH-AEC1 ** qfn-18 (2.5mmx3.5mm) * for tape & reel, add suffix ?z (e.g. mpq2166gd?z) ** under qualification *** under qualification, wettable flank top marking (mpq2166gd & mpq2166gd-aec1) aqf: product code of mpq2166gd and mpq2166gd-aec1 y: year code ww: week code lll: lot number top marking (mpq2166gde-aec1) axf: product code of mpq2166gde-aec1 y: year code ww: week code lll: lot number top marking (mpq2166grh&MPQ2166GRH-AEC1) avp: product code of mpq2166 grh and MPQ2166GRH-AEC1 y: year code ww: week code lll: lot number
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 4 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package reference top view qfn-18 (2.5mmx3.5mm) qfn-18 (2mmx3mm) absolute maxi mum ratings (1) supply voltage (v in ) .................................... 6.5v v sw ........................................ -0.3v to v in + 0.3v all other pins ................................ -0.3v to +6.5v junction temperature ................................ 150c lead temperature ..................................... 260c continuous power dissipation (t a = +25c) (2) qfn-18 (2mmx3mm) ............................... 1.78w qfn-18 (2.5mmx3.5mm) ........................... 2.5w recommended operating conditions supply voltage (v in ) ........................... 2.7v to 6v output voltage (v out ) ...................... 0.6v to 5.5v operating junction temp. .......... -40c to +125c thermal resistance (3) ja jc qfn-18 (2mmx3mm)..............70 ?? 15 ?. c/w qfn-18 (2.5mmx3.5mm)........50 ?? 12 ?. c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) measured on jesd51-7, 4-layer pcb.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 5 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics v in = 5v, t j = -40c to +125c, unless otherwise noted. typical values are at t j = 25c. parameters symbol condition min typ max units supply current (quiescent) i q v in = 5v, v en = 2v, v fb = 0.65v, no switching 60 80 a shutdown current i shdn v en = 0v, ccm=gnd, t j = +25c 0 0.2 a v en = 0v, ccm=gnd t j = -40c to +85c (4) 0 1.5 a v en = 0v, ccm=gnd t j = +85c to +125c 5 a vin under-voltage lockout threshold in uvlo rising edge 2.4 2.55 v vin under-voltage lockout hysteresis in uvlo _ hys 230 mv regulated fb voltage v fb t j = +25c 0.593 0.600 0.607 v t j = -40c to +125c 0.588 0.600 0.612 v fb input current i fb v fb = 0.65v 0 50 na en high threshold v en _ h 1.6 v en low threshold v en _ l 0.4 v en input current i en v en = 2v 0 0.1 a v en = 0v 0 0.1 hs switch on resistance r dson _ p v in = 5v 55 90 m ? ls switch on resistance r dson _ n v in = 5v 20 45 m ? sw leakage current i sw _ lk v en = 0v, v in = 6v, v sw = 0v and 6v, t j = 25c -1 0 1 a hs switch current limit (4) i hs _ limit sourcing 3.4 4.5 5.6 a ls valley current limit ( 4 ) i valley 3.9 a ls switch current limit i ls _ limit sinking, ccm 1 a oscillator frequency accuracy f sw r freq = 665k 298 350 402 khz r freq = 200k 850 1000 1150 khz r freq = 51k 2700 3000 3300 khz sync frequency range f sync 0.35 3 mhz phase shift 180 degree minimum on time ( 4 ) t on _ min 55 ns minimum off time (4) t off _ min 50 ns maximum duty cycle d max 100 % thermal shutdown threshold ( 4 ) t d 175 c thermal shutdown hysteresis ( 4 ) t d _ hys 40 c soft-start charging current i ss v ss = 0v 2 3.2 5 a power good rising threshold pgood vth-hi 0.85 0.9 0.95 v fb power good falling threshold pgood vth-lo 0.77 0.82 0.87 v fb power good rising delay t pgood _ r 30 s power good falling delay t pgood _ f 40 s ccm on threshold 1.6 v ccm off threshold 0.4 v note: 4) guaranteed by design and characteri zation, not test in production.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 6 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 0 5 10 15 20 25 1 1.5 2 2.5 3 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 -40-25-10 5 20 35 50 65 80 95 110125 -40-25-10 5 20 35 50 65 80 95 110125 -40-25-10 5 20 35 50 65 80 95 110125 595 596 597 598 599 600 601 602 603 50 52 54 56 58 60 62 64 66
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 7 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. frequency vs. temperature f sw =1mhz frequency vs. temperature f sw =3mhz frequency vs. temperature f sw =350khz frequency (mhz) frequency (khz) -40-25-10 5 20 35 50 65 80 95 110125 -40-25-10 5 20 35 50 65 80 95 110125 -40-25-10 5 20 35 50 65 80 95 110125 frequency (mhz) 340 342 344 346 348 350 352 354 356 358 360 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 2.96 2.97 2.98 2.99 3 3.01 3.02 3.03 3.04
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 8 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. v out2 /ac 10mv/div. v out1 /ac 10mv/div. v sw1 5v/div. v sw2 5v/div. i l1 200ma/div. i l2 200ma/div. v out2 /ac 10mv/div. v out1 /ac 10mv/div. v sw1 5v/div. v sw2 5v/div. i l1 500ma/div. i l2 500ma/div. v out2 /ac 2mv/div. v out2 1v/div. v in 5v/div. v out1 /ac 2mv/div. v sw1 5v/div. v sw2 5v/div. v sw2 5v/div. i l1 1a/div. i l2 1a/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 1v/div. v in 5v/div. v sw2 5v/div. i l2 2a/div. v out1 1v/div. v sw1 5v/div. i l1 2a/div. v out2 1v/div. v in 2v/div. v sw2 5v/div. i l2 2a/div. v out1 1v/div. v sw1 5v/div. i l1 2a/div. v out2 1v/div. v in 5v/div. v sw2 5v/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 /ac 10mv/div. v out1 /ac 10mv/div. v sw1 5v/div. v sw2 5v/div. i l1 1a/div. i l2 1a/div. v out2 1v/div. v in 5v/div. v sw2 2v/div. i l2 50ma/div. v out1 1v/div. v sw1 2v/div. i l1 50ma/div.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 9 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 1a/div. v out1 1v/div. v sw1 5v/div. i l1 1a/div. v out2 1v/div. v en 2v/div. v sw2 2v/div. i l2 50ma/div. v out1 1v/div. v sw1 2v/div. i l1 50ma/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 2a/div. v out1 1v/div. v sw1 5v/div. i l1 2a/div. v out2 1v/div. v in 5v/div. v sw2 5v/div. i l2 500ma/div. v out1 1v/div. v sw1 5v/div. i l1 500ma/div. v out2 1v/div. v in 5v/div. v sw2 5v/div. i l2 2a/div. v out1 1v/div. v sw1 5v/div. i l1 2a/div. v out2 1v/div. v in 2v/div. v sw2 5v/div. i l2 1a/div. v out1 1v/div. i l1 1a/div.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 10 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 2a/div. v out1 1v/div. v sw1 5v/div. i l1 2a/div. v out2 1v/div. v en 2v/div. v sw2 5v/div. i l2 1a/div. v out1 1v/div. v sw1 5v/div. i l1 1a/div.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 11 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, v out1 = 1.8v, v out2 = 1.2v, l1 = l2 = 1.5h, f sw = 2.25mhz, t a = 25c, unless otherwise noted. v out1 /ac 200mv/div. v sw1 5v/div. i l1 2a/div. v out2 /ac 100mv/div. v sw2 5v/div. i l2 2a/div. v out2 1v/div. v sw2 5v/div. i l2 5a/div. v out1 1v/div. v sw1 5v/div. i l1 5a/div. v sw1 5v/div. i l1 2a/div. v sw2 5v/div. i l2 2a/div. v out1 /ac 100mv/div. v sw1 5v/div. i l1 1a/div. v out2 /ac 100mv/div. v sw2 5v/div. i l2 1a/div. v out1 /ac 200mv/div. v sw1 5v/div. i l1 2a/div. v out2 /ac 200mv/div. v sw2 5v/div. i l2 2a/div. v out1 /ac 100mv/div. v sw1 5v/div. i l1 1a/div. v out2 /ac 100mv/div. i l2 1a/div.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 12 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions package pin # name description 1 pgnd2 power ground of channel 2. connect pgnd2 with larger copper areas to the negative terminals of the input and output capacitors. 2 sw2 switch node connection to the inductor for channel 2. sw2 connects to the internal high- and low-side power mosfet switches of the channel 2 buck. 3 vin2 input supply for channel 2. a decoupling capacitor to ground is required close to vin2 to reduce switching spikes. 4 ss2 soft start for channel 2. 5 fb2 feedback for channel 2. fb2 is the input to the error amplifier of channel 2. an external resistive divider connects fb 2 between the output and ground. the voltage on fb2 compares to the internal 0.6v referenc e to set the regulation voltage of channel 2. 6 agnd analog ground. connect agnd to pgnd externally. 7 vcc power supply to the internal regulator for both channels. decouple with a 0.1f to 1f capacitor between vcc and agnd. 8 ccm aam or forced ccm control. pull ccm high to enter forced ccm mode; pull ccm low to enter aam mode at light load. do not float ccm. 9 fb1 feedback for channel 1. fb1 is the input to the error amplifier of channel 1. an external resistive divider connects fb 1 between the output and gnd. the voltage on fb1 compares to the internal 0.6v referenc e to set the regulation voltage of channel 1. 10 ss1 soft start for channel 1. 11 vin1 input supply for channel 1. a decoupling capacitor to ground is required close to vin1 to reduce switching spikes. 12 sw1 switch node connection to the inductor for channel 1. sw1 connects to the internal high- and low-side power mosfet switches of the channel 1 buck. 13 pgnd1 power ground of channel 1. connect pgnd1 with larger copper areas to the negative terminals of the input and output capacitors. 14 pg1 power good for channel 1. 15 en1 enable control for channel 1. 16 freq frequency set. connect a resistor to gnd to set the switching frequency. the switching frequency can be synchronized by an external clock via freq. 17 en2 enable control for channel 2. 18 pg2 power good for channel 2.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 13 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. block diagram figure 1: functional block diagram
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 14 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. operation the mpq2166 is a fully integrated, dual- channel, synchronous, step-down converter. both channels use peak-current-mode control with internal compensation for fast transient response and cycle-to-cycle current limit. the mpq2166 is optimized for low-voltage, portable applications where efficiency and small size are critical. 180 out-of-phase operation the mpq2166 operates the two channels in 180 out-of-phase operation to reduce input current ripple so a smaller input bypass capacitor can be used. when both channels operate in ccm, two internal clocks are used (see figure 2). the high-side mosfet is turned on at the clock rising edge of the corresponding channel. figure 2: 180 out-of-phase operation at low dropout, when the switching frequency is stretched out for each channel, the mpq2166 runs at a fixed-off time with its own independent switching frequency. after the input voltage rises high again, frequency stretch mode ends, and pwm mode resumes and synchronizes with the master oscillator for out-of-phase operation. light-load operation in light-load condition, the mpq2166 can work in two different operating modes by setting ccm to different statuses. the mpq2166 works in forced continuous conduction mode (ccm) when the ccm pin is pulled higher than 1.6v. the mpq2166 works with fixed frequency from no load to full load in this mode. the advantage of ccm is the controllable frequency and lower output ripple at light load. the shutdown current in forced ccm mode (50 a at 3.3v) is much higher than aam mode due to some internal circuits are active. it is recommended to pull ccm pin low when part is shutdown if the high shutdown current is cared. the mpq2166 works in advanced asynchronous mode (aam) when ccm is pulled lower than 0.4v. aam is used to optimize efficiency during light-load and no-load conditions. when aam mode is enabled, the mpq2166 first enters non-synchronous operation as the inductor current approaches zero at light load. if the load decreases further or is at no load, which makes the internal comp voltage (v comp ) decrease to the set value, then the mpq2166 enters aam. in aam, the internal clock is reset whenever v comp crosses over the set value, and the crossover time is taken as the benchmark of the next clock. when the load increases and v comp is higher than the set value, the operation mode is in dcm or ccm, which has a constant switching frequency. figure 3: aam mode and forced ccm mode soft start (ss) the mpq2166 has a built-in soft start that ramps up the output voltage at a controlled slew rate, preventing an overshoot at start-up. the soft-start time is about 0.5ms, typically. the soft-start time can also be programmed by an external capacitor connected to ss, shown in equation (1): ?? ?? ?? ?? a i v v nf c ms t ss rff ss ss ? ? (1) where c ss is the external ss capacitor, v ref is the internal reference voltage (0.6v), and i ss is the 3.2a ss charge current.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 15 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. oscillator and sync function the internal oscillator frequency is set by a single external resistor (r freq ) connected between freq and ground. the frequency setting resistor should be located close to the device. the relationship between the oscillator frequency and r freq is shown in figure 4. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 10 100 1000 figure 4: f sw vs. r freq freq can also be used to synchronize the internal oscillator to an external clock. the rising edge of the channel 1 clock is synchronized to the external clock rising edge, while the channel 2 clock remains at 180 out- of-phase to channel 1. the recommended external sync frequency is in the range of 350khz to 3mhz. while there is no pulse width requirement, note that there is always parasitic capacitance of the pad there, so if the pulse width is too short, a clear rising and falling edge may not be seen. the pulse is recommended to be longer than 100ns. power good (pg) the mpq2166 has one power good (pg) output to indicate normal operation after the soft-start time. pg is the open drain of an internal mosfet. it should be connected to vin, vcc, or an external voltage source through a resistor (i.e.: 100k ? ). after the input voltage is applied, the mosfet is turned on and pg is pulled to gnd before ss is ready. after the fb voltage reaches 82% of the reference voltage (v ref ), the mosfet turns off and pg is pulled high by an external voltage source. when the fb voltage drops to 76% of v ref , the pg voltage is pulled to gnd to indicate a failure output. current limit and short circuit each channel of the mpq2166 has a typical 4.5a current limit for the high-side switch. when the current limit condition is sustained for a pre- defined period of time, the mpq2166 treats this as a short and attempts to recover with hiccup mode. in hiccup mode, the mpq2166 disables the output power stage, slowly discharges the soft- start cap, and soft starts automatically. if the short-circuit condition still remains, the mpq2166 repeats this operation cycle until the short circuit is removed and the output rises back to regulation levels. dropout operation the mpq2166 allows the high-side switch to remain on for more than one switching cycle and increases the duty cycle while the input voltage drops down to the output voltage. when the duty cycle reaches 100%, the high-side switch is on to deliver current to the output up to its current limit. the output voltage is then the difference between the input voltage and the voltage drop across the main switch and the inductor.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 16 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. application information setting the output voltage the external resistor divider sets the output voltage. the feedback resistor (r1) also sets the feedback loop bandwidth with the internal compensation (see figure 5). figure 5: external resistor divider in the case of ceramic capacitors used as output capacitors (c o ), the feedback loop bandwidth (f c ) is no higher than 1/10 of the switching frequency for optimal transient performance and good phase margin. if an electrolytic capacitor is used, the loop bandwidth is no higher than 1/4 of the esr zero frequency (f esr ). f esr can be calculated by equation (2): esr esr o 1 f 2r c ? ?? ? (2) for example, choose f c = 80khz with a ceramic capacitor and c o = 22 f. r1 is estimated to be 100k ? . r2 can then be calculated with equation (3): out r1 r2 v 1 0.6v ? ? (3) use table 1 to select resistor values based on different output voltages. table 1: resistor selection vs. output voltage setting v out r1 r2 1.2v 100k ? 100k ? 1.5v 100k ? 66.5k ? 1.8v 100k ? 49.9k ? 2.5v 100k ? 31.6k ? 3.3v 100k ? 22.1k ? inductor selection an inductor with a dc current rating at least 25% higher than the maximum load current is recommended for most applications. for best efficiency, the inductor dc resistance should be less than 20m ? . for most designs, the inductance value can be derived from equation (4): sw l in out in out f i v ) v - (v v l ? ? ? ? ? (4) where ? i l is inductor ripple current. choose the inductor ripple current to be approximately 30% of the maximum load current. the maximum inductor peak current can be calculated with equation (5): l l(max) load ? i i=i+ 2 (5) input capacitor selection the input capacitor reduces the surge current drawn from the input and the switching noise from the device. the input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high- frequency switching current from passing to the input source. ceramic capacitors with x5r or x7r dielectrics are highly recommended because of their low esr and small temperature coefficients. for most applications, a 22f capacitor is sufficient. output capacitor selection the output capacitor (c o ) keeps the output voltage ripple small and ensures a stable regulation loop. the output capacitor impedance should be low at the switching frequency. use ceramic capacitors with x5r or x7r dielectrics. if an electrolytic capacitor is used, pay close attention to the output ripple voltage, extra heating, and the selection of the upper feedback resistor due to the large esr of electrolytic capacitor (refer to the setting the output voltage section). the output ripple ( ? v out ) can be approximated with equation (6): ) 8 1 ( co f esr f l v ) v - (v v v sw sw in out in out out ? ? ? ? ? ? ? ? ? (6)
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 17 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. power dissipation ic power dissipation is important in circuit design, not only because of efficiency concerns, but also because of the chip?s thermal requirements. several parameters influence power dissipation, such as conduction loss (cond), dead time (dt), switching loss (sw), mosfet driver current (dr), and supply current (s). based on these parameters, we can estimate the power loss with equation (7): s dr sw dt cond loss p p p p p p ? ? ? ? ? (7) thermal regulation changes in ic temperatures change the electrical characteristics, especially when the temperature exceeds the ic?s recommended operating range. managing the ic?s temperature requires additional considerations to ensure that the ic runs within the maximum allowable temperature junction. specific layout designs can improve the thermal profile while limiting costs to either the efficiency or operating range. for the mpq2166, connect the ground pin on the package to a ground plane on top of the pcb to use this plane as a heat sink. connect this ground plane to the ground planes beneath the ic using vias to improve heat dissipation. however, given that these ground planes can introduce unwanted emi noise and occupy valuable pcb space, design their size and shape to match the thermal resistance requirement. connecting the ground pin to a heat sink cannot guarantee that the ic will not exceed its recommended temperature limits (i.e.: the ambient temperature exceeds the ic?s temperature limits). if the ambient air temperature approaches the ic?s temperature limit, the ic can be de-rated to operate using less power and help prevent thermal damage and unwanted electrical characteristics.
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 18 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pcb layout guidelines (5) efficient pcb layout is critical for stable operation. a four-layer layout is strongly recommended to achieve better thermal performance. for best results, refer to figure 6 and follow the guidelines below. 1. place the high-current paths (pgnd, vin, and sw) very close to the device with short, direct, and wide traces. 2. place input capacitors on both vin sides and as close to vin and pgnd as possible. 3. place the decoupling capacitor as close to vcc and agnd as possible. 4. keep the switching node sw short and away from the feedback network. 5. place the external feedback resistors next to fb. do not place vias on the fb trace. 6. connect pgnd to a large copper area to achieve better thermal performance. top layer inner layer 1 inner layer 2 bottom layer figure 6: recommended pcb layout note: 5) the recommended pcb layout is based on figure7
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 19 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits 1 2 3 4 13 12 11 10 5 6 pgnd1 sw1 vin1 fb1 fb2 vin2 sw2 pgnd2 7 8 9 18 17 16 15 14 ss1 pg1 freq pg2 ss2 en2 ccm agnd en1 vcc mpq2166 22uf c1a 16v 22uf 16v 2.7v-6v en2 0.1uf c1b 16v en1 100k r4 100k r9 75k r11 c4 50v c3 jp1 vcc agnd ccm aam 10 r7 100k r8 c1c c1d 22uf c2c 22uf c2d vout2 1.5uh l2 10 r5 100k r6 22uf c2a vout1 1.5uh l1 22uf c2b vcc 0805 0805 0805 0805 16v 16v 0805 0805 16v 16v 0805 0805 1.5nf 50v 1.5nf 1.2v/2a 1.8v/2a 100k r3 100k r1 0.1uf 16v vin gnd 0.1uf c5 chb cha 100k r12 49.9k r18 nc c11 r17 nc c8 r19 r16 100k nc r15 100k nc pg2 pg1 figure 7: 2a/2a application circuit figure 8: 3a/1a application circuit
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 20 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-18 (2.5mmx3.5mm)
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss mpq2166 rev. 1.11 www.monolithicpower.com 21 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-18 (2mmx3mm) non-wettable flank
mpq2166 ? 6v, dual 2a/2a or 3a/1a, sync, buck regulator with pg and ss notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mpq2166 rev. 1.11 www.monolithicpower.com 22 5/31/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-18 (2mmx3mm) wettable flank side view bottom view pin 1 id marking top view pin 1 id index area recommended land pattern pin 1 id 0.15x0.10 typ 0.15x0.10 section a-a note: 1) the lead side is wettable. 2) all dimensions are in millimeters. 3) lead coplanarity shall be 0.08 millimeters max. 4) jedec reference is mo-220. 5) drawing is not to scale.

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